The present invention relates to a video system with power reduction.
Existing video coding standards, such as H.264/AVC, generally provide relatively high coding efficiency at the expense of increased computational complexity. The relatively high computational complexity has resulted in significant power consumption, which is especially problematic for low power devices such as cellular phones.
Power reduction is generally achieved by using two primary techniques. The first technique for power reduction is opportunistic, where a video coding system reduces its processing capability when operating on a sequence that is easy to decode. This reduction in processing capability may be achieved by frequency scaling, voltage scaling, on-chip data pre-fetching (caching), and/or a systematic idling strategy. In many cases the resulting decoder operation conforms to the standard. The second technique for power reduction is to discard frame or image data during the decoding process. This typically allows for more significant power savings but generally at the expense of visible degradation in the image quality. In addition, in many cases the resulting decoder operation does not conform to the standard.